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ISCA
2010
IEEE
219views Hardware» more  ISCA 2010»
14 years 4 months ago
Using hardware vulnerability factors to enhance AVF analysis
Fault tolerance is now a primary design constraint for all major microprocessors. One step in determining a processor’s compliance to its failure rate target is measuring the Ar...
Vilas Sridharan, David R. Kaeli
ISCA
2010
IEEE
189views Hardware» more  ISCA 2010»
14 years 4 months ago
RETCON: transactional repair without replay
Over the past decade there has been a surge of academic and industrial interest in optimistic concurrency, i.e. the speculative parallel execution of code regions that have the se...
Colin Blundell, Arun Raghavan, Milo M. K. Martin
ISCA
2010
IEEE
214views Hardware» more  ISCA 2010»
14 years 4 months ago
Re-architecting DRAM memory systems with monolithically integrated silicon photonics
The performance of future manycore processors will only scale with the number of integrated cores if there is a corresponding increase in memory bandwidth. Projected scaling of el...
Scott Beamer, Chen Sun, Yong-Jin Kwon, Ajay Joshi,...
ISCA
2010
IEEE
192views Hardware» more  ISCA 2010»
14 years 4 months ago
NoHype: virtualized cloud infrastructure without the virtualization
Cloud computing is a disruptive trend that is changing the way we use computers. The key underlying technology in cloud infrastructures is virtualization – so much so that many ...
Eric Keller, Jakub Szefer, Jennifer Rexford, Ruby ...
ISCA
2010
IEEE
205views Hardware» more  ISCA 2010»
14 years 4 months ago
The virtual write queue: coordinating DRAM and last-level cache policies
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...
ISCA
2010
IEEE
163views Hardware» more  ISCA 2010»
14 years 4 months ago
WiDGET: Wisconsin decoupled grid execution tiles
The recent paradigm shift to multi-core systems results in high system throughput within a specified power budget. However, future systems still require good single thread perfor...
Yasuko Watanabe, John D. Davis, David A. Wood
ISCA
2010
IEEE
240views Hardware» more  ISCA 2010»
14 years 4 months ago
Modeling critical sections in Amdahl's law and its implications for multicore design
This paper presents a fundamental law for parallel performance: it shows that parallel performance is not only limited by sequential code (as suggested by Amdahl’s law) but is a...
Stijn Eyerman, Lieven Eeckhout