— With increasing reliability concerns for current and next generation VLSI technologies, fault-tolerance is fast becoming an integral part of system-on-chip (SoC) and multicore ...
- This paper presents a 2GS/s 10-bit CMOS digital-to-analog converter (DAC). This DAC consists of a unit current-cell matrix for 6MSBs and another unit current-cell matrix for 4L...
— We present theory, design and measurement results for an on-line histogram equalization algorithm implemented on a 750MS/s 6b flash analog to digital converter in standard 0.3...
Abstract— An integrated CMOS RF power detector for wideband systems that does not require additional processing steps is presented. The received signal modulates the resistance o...
Kenneth A. Townsend, James W. Haslett, John Nielse...
— This paper presents performance and area evaluation of a homogeneous multiprocessor communication system based on network-on-chip (NoC) in FPGA platforms. Two homogenous chip m...
Henrique C. Freitas, Dalton M. Colombo, Fernanda L...
—The paper presents architecture and synthesis results for an organic computing hardware for smart CMOS camera chips. The organic behavior in the chip hardware is based on distri...
Dietmar Fey, Marcus Komann, Frank Schurz, Andreas ...
—Time-interleaved analog-to-digital converters (TIADC) require mismatch calibration to achieve high signal-to-noise ratios. In this paper, we present a new blind technique for M=...
— The paper formulates and solves the problem of optimizing power flows in polyphase systems with significant source (line) impedance. We present two fundamental performance bo...
— Reducing the leakage power in embedded SRAM memories is critical for low-power applications. Raising the source voltage of SRAM cells in standby mode reduces the leakage curren...