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    ISLPED
    2005
    ACM
    86views Hardware» more  ISLPED 2005»
    An evaluation of code and data optimizations in the context of disk power reduction
    14 years 7 months ago
    An evaluation of code and data optimizations in the context of disk power reduction
    Download  www.cse.psu.edu
    Disk power management is becoming increasingly important in high-end server and cluster type of environments that execute dataintensive applications. While hardware-only approache...
    Mahmut T. Kandemir, Seung Woo Son, Guangyu Chen
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    ISLPED
    2005
    ACM
    101views Hardware» more  ISLPED 2005»
    Defocus-aware leakage estimation and control
    14 years 7 months ago
    Defocus-aware leakage estimation and control
    Download  vlsicad.ucsd.edu
    Leakage power is one of the most critical issues for ultra-deep submicron technology. Subthreshold leakage depends exponentially on linewidth, and consequently variation in linewi...
    Andrew B. Kahng, Swamy Muddu, Puneet Sharma
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    ISLPED
    2005
    ACM
    123views Hardware» more  ISLPED 2005»
    Coordinated, distributed, formal energy management of chip multiprocessors
    14 years 7 months ago
    Coordinated, distributed, formal energy management of chip multiprocessors
    Download  www.princeton.edu
    Designers are moving toward chip-multiprocessors (CMPs) to leverage application parallelism for higher performance while keeping design complexity under control. However, to date,...
    Philo Juang, Qiang Wu, Li-Shiuan Peh, Margaret Mar...
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    ISLPED
    2005
    ACM
    68views Hardware» more  ISLPED 2005»
    Low power SRAM techniques for handheld products
    14 years 7 months ago
    Low power SRAM techniques for handheld products
    Download  www.cecs.uci.edu
    SRAM leakage constitutes a significant portion of the standby power budget of modern SoC products for handheld applications such as PDA and cellular phones. NMOS and PMOS reverse ...
    Rabiul Islam, Adam Brand, Dave Lippincott
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    ISLPED
    2005
    ACM
    103views Hardware» more  ISLPED 2005»
    A non-uniform cache architecture for low power system design
    14 years 7 months ago
    A non-uniform cache architecture for low power system design
    Download  www.c.csce.kyushu-u.ac.jp
    This paper proposes a non-uniform cache architecture for reducing the power consumption of memory systems. The nonuniform cache allows having different associativity values (i.e.,...
    Tohru Ishihara, Farzan Fallah
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    ISLPED
    2005
    ACM
    178views Hardware» more  ISLPED 2005»
    Energy efficient strategies for deployment of a two-level wireless sensor network
    14 years 7 months ago
    Energy efficient strategies for deployment of a two-level wireless sensor network
    Download  atrak.usc.edu
    We investigate and develop energy-efficient strategies for deployment of wireless sensor networks (WSN) for the purpose of monitoring some phenomenon of interest in a coverage reg...
    Ali Iranli, Morteza Maleki, Massoud Pedram
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    ISLPED
    2005
    ACM
    150views Hardware» more  ISLPED 2005»
    Fast configurable-cache tuning with a unified second-level cache
    14 years 7 months ago
    Fast configurable-cache tuning with a unified second-level cache
    Download  www.cs.ucr.edu
    Tuning a configurable cache subsystem to an application can greatly reduce memory hierarchy energy consumption. Previous tuning methods use a level one configurable cache only, or...
    Ann Gordon-Ross, Frank Vahid, Nikil D. Dutt
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    ISLPED
    2005
    ACM
    63views Hardware» more  ISLPED 2005»
    Inter-program optimizations for conserving disk energy
    14 years 7 months ago
    Inter-program optimizations for conserving disk energy
    Download  www.cs.rutgers.edu
    Previous work has shown that intra-program optimizations, i.e., optimizations performed on individual programs in isolation, can be very effective in reducing disk energy in stre...
    Jerry Hom, Ulrich Kremer
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    ISLPED
    2005
    ACM
    108views Hardware» more  ISLPED 2005»
    Replacing global wires with an on-chip network: a power analysis
    14 years 7 months ago
    Replacing global wires with an on-chip network: a power analysis
    Download  groups.csail.mit.edu
    This paper explores the power implications of replacing global chip wires with an on-chip network. We optimize network links by varying repeater spacing, link pipelining, and volt...
    Seongmoo Heo, Krste Asanovic
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    ISLPED
    2005
    ACM
    91views Hardware» more  ISLPED 2005»
    LAP: a logic activity packing methodology for leakage power-tolerant FPGAs
    14 years 7 months ago
    LAP: a logic activity packing methodology for leakage power-tolerant FPGAs
    Download  www.cecs.uci.edu
    As FPGAs enter the nanometer regime, several modifications are needed to reduce the increasing leakage power dissipation. Hence, this work presents some modifications to the FPG...
    Hassan Hassan, Mohab Anis, Mohamed I. Elmasry
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