In this paper we present a parasitic aware, process variation tolerant optimization methodology that may be applied to nanoscale circuits to ensure better yield. A currentstarved voltage controlled oscillator (VCO) is treated as a case study and to the best of the authors’ knowledge, this is the first VCO design that accounts for both parasitic degradation and process variation together. The physical design of the VCO is carried out in a generic 90nm Salicide
Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos