The evolution of deep submicron technologies allows the development of increasingly complex Systems on a Chip (SoC). However, this evolution is rendering less viable some well-est...
Julian J. H. Pontes, Matheus T. Moreira, Rafael So...
A structured ASIC has some arrays of pre-fabricated yet configurable logic blocks (CLBs) with/without a regular routing fabric. In this paper, we propose a standard cell like via-...
The share of leakage in cache power consumption increases with technology scaling. Choosing a higher threshold voltage (Vth) and/or gate-oxide thickness (Tox) for cache transistor...
Subthreshold circuits exhibit ultra-low energy per operation at the expense of increased delay. In this contribution, the impact of technology scaling on digital subthreshold circ...
David Bol, Renaud Ambroise, Denis Flandre, Jean-Di...
The number of edge devices connected to the Internet is increasing at a rapid rate. To maintain network connectivity, the majority of these devices remain completely powered on wh...
Karthik Sabhanatarajan, Ann Gordon-Ross, Mark Oden...
Future embedded systems will integrate hundreds of processors. Current design space exploration methods cannot cope with such a complexity. It is mandatory to extend these methods...
Issam Maalej, Guy Gogniat, Jean Luc Philippe, Moha...
With the advent of nanometer technologies, the design size of integrated circuits is getting larger and the operation speed is getting faster. As a consequence, test cost is becom...
Scalability of architecture, programming model and task control management will be a major challenge for future VLSI systems. In this context, homogeneous MPSOC is a seducing appr...
Nicolas Saint-Jean, Pascal Benoit, Gilles Sassatel...
Intelligent mobile information devices require lowpower and high-performance processors. In order to reduce energy consumption with maintaining computing performance, we proposed ...