ITC
2002
IEEE
14 years 5 months ago
2002
IEEE
1 This paper presents a test input data compression technique, which can be used to reduce input test data volume, test time, and the number of required tester channels. The techni...
ITC
2002
IEEE
14 years 5 months ago
2002
IEEE
—Logic optimization is the step of the very large scale integration (VLSI) design cycle where the designer performs modifications on a design to satisfy different constraints suc...
ITC
2002
IEEE
14 years 5 months ago
2002
IEEE
Conventional fault simulation techniques for FPGAs are very complicated and time consuming. The other alternative, FPGA fault emulation technique, is incomplete, and can be used o...
ITC
2002
IEEE
14 years 5 months ago
2002
IEEE
The continued market demand for GHz processors and high-capacity communication systems results in an increasing number of low-cost high volume ICs with multi-GHz clocks and/or mul...
ITC
2002
IEEE
14 years 5 months ago
2002
IEEE
ITC
2002
IEEE
14 years 5 months ago
2002
IEEE
: We present a Built-In Self-Test (BIST)-based diagnostic approach for the programmable interconnect resources in Field Programmable Gate Arrays (FPGAs) that can be used for either...
ITC
2002
IEEE
14 years 5 months ago
2002
IEEE
ITC
2002
IEEE
14 years 5 months ago
2002
IEEE
Significant reductions in test application times can be achieved through parallelizing core tests; however, simultaneous test of various cores may result in exceeding power thres...
ITC
2002
IEEE
14 years 5 months ago
2002
IEEE
ITC
2002
IEEE
14 years 5 months ago
2002
IEEE
