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ICDCS
2012
IEEE
12 years 1 months ago
eTransform: Transforming Enterprise Data Centers by Automated Consolidation
Abstract—Modern day enterprises have a large IT infrastructure comprising thousands of applications running on servers housed in tens of data centers geographically spread out. T...
Rahul Singh, Prashant J. Shenoy, K. K. Ramakrishna...
CORR
2011
Springer
194views Education» more  CORR 2011»
13 years 6 months ago
Energy-Latency Tradeoff for In-Network Function Computation in Random Networks
—The problem of designing policies for in-network function computation with minimum energy consumption subject to a latency constraint is considered. The scaling behavior of the ...
Paul N. Balister, Béla Bollobás, Ani...
ESA
2006
Springer
140views Algorithms» more  ESA 2006»
14 years 3 months ago
Latency Constrained Aggregation in Sensor Networks
A sensor network consists of sensing devices which may exchange data through wireless communication. A particular feature of sensor networks is that they are highly energy constrai...
Luca Becchetti, Peter Korteweg, Alberto Marchetti-...
ISLPED
2005
ACM
103views Hardware» more  ISLPED 2005»
14 years 5 months ago
A technique for low energy mapping and routing in network-on-chip architectures
Network-on-chip (NoC) has been proposed as a solution for the global communication challenges of System-on-chip (SoC) design in the nanoscale technologies. NoC design with mesh ba...
Krishnan Srinivasan, Karam S. Chatha
DATE
2008
IEEE
158views Hardware» more  DATE 2008»
14 years 6 months ago
Performance Analysis of SoC Architectures Based on Latency-Rate Servers
This paper presents a method for static performance analysis of SoC architectures. The method is based on a network calculus theory known as LR servers. This network calculus is e...
Jelte Peter Vink, Kees van Berkel, Pieter van der ...
ICETET
2009
IEEE
14 years 6 months ago
Low Energy Tree Based Network on Chip Architectures Using Homogeneous Routers for Bandwidth and Latency Constrained Multimedia A
Abstract— Design of Network on chip architectures for multimedia applications is being widely studied. This involves design decisions at various levels of hierarchy. Topology des...
Deepak Majeti, Aditya Pasalapudi, Kishore Yalamanc...
DAC
2006
ACM
15 years 14 days ago
An efficient and versatile scheduling algorithm based on SDC formulation
Scheduling plays a central role in the behavioral synthesis process, which automatically compiles high-level specifications into optimized hardware implementations. However, most ...
Jason Cong, Zhiru Zhang