ICCAD
2003
IEEE
14 years 10 months ago
2003
IEEE
This paper proposes for latency insensitive systems a performance optimization technique called channel buffer queue sizing, which is performed after relay station insertion in th...
DATE
2005
IEEE
14 years 10 months ago
2005
IEEE
In this paper we present our contribution in terms of synchronization processor for a SoC design methodology based on the theory of the latency insensitive systems (LIS) of Carlon...