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    ASPDAC
    2010
    ACM
    135views Hardware» more  ASPDAC 2010»
    Statistical timing verification for transparently latched circuits through structural graph traversal
    13 years 9 months ago
    Statistical timing verification for transparently latched circuits through structural graph traversal
    Download  www.ece.iit.edu
    Level-sensitive transparent latches are widely used in high-performance sequential circuit designs. Under process variations, the timing of a transparently latched circuit will ada...
    Xingliang Yuan, Jia Wang
    claim paper
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