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ISQED
2005
IEEE
76views Hardware» more  ISQED 2005»
14 years 5 months ago
Technology Mapping for Reliability Enhancement in Logic Synthesis
Abstract— Reliability enhancements are traditionally implemented through redundancies at the system level or through the use of harden-cell-designs at the circuit level. Reliabil...
Zhaojun Wo, Israel Koren
ICCAD
2005
IEEE
98views Hardware» more  ICCAD 2005»
14 years 8 months ago
Clustering for processing rate optimization
Clustering (or partitioning) is a crucial step between logic synthesis and physical design in the layout of a large scale design. A design verified at the logic synthesis level m...
Chuan Lin, Jia Wang, Hai Zhou