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SC
2004
ACM
14 years 5 months ago
Using Hardware Counters to Automatically Improve Memory Performance
In this paper, we introduce a profile-driven online page migration scheme and investigate its impact on the performance of multithreaded applications. We use lightweight, inexpens...
Mustafa M. Tikir, Jeffrey K. Hollingsworth
ASPLOS
2004
ACM
14 years 5 months ago
Compiler orchestrated prefetching via speculation and predication
This paper introduces a compiler-orchestrated prefetching system as a unified framework geared toward ameliorating the gap between processing speeds and memory access latencies. ...
Rodric M. Rabbah, Hariharan Sandanagobalane, Mongk...
WEA
2005
Springer
120views Algorithms» more  WEA 2005»
14 years 5 months ago
Distilling Router Data Analysis for Faster and Simpler Dynamic IP Lookup Algorithms
Abstract. We consider the problem of fast IP address lookup in the forwarding engines of Internet routers. We analyze over 2400 public snapshots of routing tables collected over ...
Filippo Geraci, Roberto Grossi
STORAGESS
2005
ACM
14 years 5 months ago
An electric fence for kernel buffers
Improper access of data buffers is one of the most common errors in programs written in assembler, C, C++, and several other languages. Existing programs and OSs frequently acces...
Nikolai Joukov, Aditya Kashyap, Gopalan Sivathanu,...
CODES
2005
IEEE
14 years 5 months ago
SOMA: a tool for synthesizing and optimizing memory accesses in ASICs
Arbitrary memory dependencies and variable latency memory systems are major obstacles to the synthesis of large-scale ASIC systems in high-level synthesis. This paper presents SOM...
Girish Venkataramani, Tiberiu Chelcea, Seth Copen ...
ICCS
2007
Springer
14 years 6 months ago
Automatic Memory Access Analysis with Periscope
Periscope is a distributed automatic online performance analysis system for large scale parallel systems. It consists of a set of analysis agents distributed on the parallel machin...
Michael Gerndt, Edmond Kereku
MICRO
2007
IEEE
139views Hardware» more  MICRO 2007»
14 years 6 months ago
Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors
DRAM memory is a major resource shared among cores in a chip multiprocessor (CMP) system. Memory requests from different threads can interfere with each other. Existing memory acc...
Onur Mutlu, Thomas Moscibroda
SEUS
2009
IEEE
14 years 6 months ago
A Single-Path Chip-Multiprocessor System
Abstract. In this paper we explore the combination of a time-predictable chipmultiprocessor system with the single-path programming paradigm. Time-sliced arbitration of the main me...
Martin Schoeberl, Peter P. Puschner, Raimund Kirne...
ESSOS
2009
Springer
14 years 6 months ago
MEDS: The Memory Error Detection System
Abstract. Memory errors continue to be a major source of software failure. To address this issue, we present MEDS (Memory Error Detection System), a system for detecting memory err...
Jason Hiser, Clark L. Coleman, Michele Co, Jack W....
ARC
2010
Springer
144views Hardware» more  ARC 2010»
14 years 6 months ago
QUAD - A Memory Access Pattern Analyser
In this paper, we present the Quantitative Usage Analysis of Data (QUAD) tool, a sophisticated memory access tracing tool that provides a comprehensive quantitative analysis of mem...
S. Arash Ostadzadeh, Roel Meeuws, Carlo Galuzzi, K...