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CAV
2010
Springer
179views Hardware» more  CAV 2010»
13 years 11 months ago
Generating Litmus Tests for Contrasting Memory Consistency Models
Well-defined memory consistency models are necessary for writing correct parallel software. Developing and understanding formal specifications of hardware memory models is a chal...
Sela Mador-Haim, Rajeev Alur, Milo M. K. Martin
ISCA
1998
IEEE
123views Hardware» more  ISCA 1998»
13 years 12 months ago
Weak Ordering - A New Definition
A memory model for a shared memory, multiprocessor commonly and often implicitly assumed by programmers is that of sequential consistency. This model guarantees that all memory ac...
Sarita V. Adve, Mark D. Hill
DATE
2002
IEEE
84views Hardware» more  DATE 2002»
14 years 16 days ago
Performance-Area Trade-Off of Address Generators for Address Decoder-Decoupled Memory
Multimedia applications are characterized by a large number of data accesses and complex array index manipulations. The built-in address decoder in the RAM memory model commonly u...
Sambuddhi Hettiaratchi, Peter Y. K. Cheung, Thomas...
PLDI
2010
ACM
14 years 20 days ago
Adversarial memory for detecting destructive races
Multithreaded programs are notoriously prone to race conditions, a problem exacerbated by the widespread adoption of multi-core processors with complex memory models and cache coh...
Cormac Flanagan, Stephen N. Freund
CHARME
2003
Springer
196views Hardware» more  CHARME 2003»
14 years 25 days ago
Analyzing the Intel Itanium Memory Ordering Rules Using Logic Programming and SAT
We present a non-operational approach to specifying and analyzing shared memory consistency models. The method uses higher order logic to capture a complete set of ordering constra...
Yue Yang, Ganesh Gopalakrishnan, Gary Lindstrom, K...
ICFEM
2004
Springer
14 years 29 days ago
Memory-Model-Sensitive Data Race Analysis
Abstract. We present a “memory-model-sensitive” approach to validating correctness properties for multithreaded programs. Our key insight is that by specifying both the inter-t...
Yue Yang, Ganesh Gopalakrishnan, Gary Lindstrom
ASIAN
2004
Springer
150views Algorithms» more  ASIAN 2004»
14 years 1 months ago
Concurrent Constraint-Based Memory Machines: A Framework for Java Memory Models
A central problem in extending the von Neumann architecture to petaflop computers with millions of hardware threads and with a shared memory is defining the memory model [Lam79,...
Vijay A. Saraswat
IPPS
2005
IEEE
14 years 1 months ago
Fast Address Translation Techniques for Distributed Shared Memory Compilers
The Distributed Shared Memory (DSM) model is designed to leverage the ease of programming of the shared memory paradigm, while enabling the highperformance by expressing locality ...
François Cantonnet, Tarek A. El-Ghazawi, Pa...
ACMMSP
2006
ACM
250views Hardware» more  ACMMSP 2006»
14 years 1 months ago
What do high-level memory models mean for transactions?
Many people have proposed adding transactions, or atomic blocks, to type-safe high-level programming languages. However, researchers have not considered the semantics of transacti...
Dan Grossman, Jeremy Manson, William Pugh
ECRTS
2006
IEEE
14 years 1 months ago
Real-Time Memory Management: Life and Times
As real-time and embedded systems become increasingly large and complex, the traditional strictly static approach to memory management begins to prove untenable. The challenge is ...
Andrew Borg, Andy J. Wellings, Christopher D. Gill...