FPGA
2003
ACM
14 years 3 days ago
2003
ACM
How does multilevel metalization impact the design of FPGA interconnect? The availability of a growing number of metal layers presents the opportunity to use wiring in the thirddi...
ISQED
2005
IEEE
14 years 14 days ago
2005
IEEE
Due to the rapid development of manufacturing process technology and tight marketing schedule, the chip design and manufacturing always work toward an integrated solution to achie...
ASPDAC
2006
ACM
14 years 26 days ago
2006
ACM
—As the VLSI manufacturing technology advances into the deep sub-micron(DSM) era, the mask cost can reach one or two million dollars. Multiple project wafers (MPW) which put diï¬...
MTDT
2006
IEEE
14 years 27 days ago
2006
IEEE
We present a ROM compiler programmable from via 1 to via n – 2, where n is the number of metal layers. The layer on which the code via is landed can be selected by the user. Wit...