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MICRO
2007
IEEE
108views Hardware» more  MICRO 2007»
13 years 12 months ago
Wagging Wikipedia's long tail
Shane Greenstein
MICRO
2007
IEEE
113views Hardware» more  MICRO 2007»
13 years 12 months ago
The High Cost of a Cheap Lesson
y abstract, it is grounded in the experience of many markets. As I will illustrate, it explains much strategic behavior. Information spreads With a bit of effort, any technically s...
Shane Greenstein
MICRO
2007
IEEE
82views Hardware» more  MICRO 2007»
13 years 12 months ago
Mixing It Up
David H. Albonesi
MICRO
2007
IEEE
71views Hardware» more  MICRO 2007»
14 years 10 days ago
Effective Optimistic-Checker Tandem Core Design through Architectural Pruning
Design complexity is rapidly becoming a limiting factor in the design of modern, high-performance microprocessors. This paper introduces an optimization technique to improve the e...
Francisco J. Mesa-Martinez, Jose Renau
MICRO
2007
IEEE
135views Hardware» more  MICRO 2007»
14 years 6 months ago
Microarchitectural Design Space Exploration Using an Architecture-Centric Approach
The microarchitectural design space of a new processor is too large for an architect to evaluate in its entirety. Even with the use of statistical simulation, evaluation of a sing...
Christophe Dubach, Timothy M. Jones, Michael F. P....
MICRO
2007
IEEE
188views Hardware» more  MICRO 2007»
14 years 6 months ago
Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding
In deep sub-micron ICs, growing amounts of ondie memory and scaling effects make embedded memories increasingly vulnerable to reliability and yield problems. As scaling progresses...
Jangwoo Kim, Nikos Hardavellas, Ken Mai, Babak Fal...
MICRO
2007
IEEE
94views Hardware» more  MICRO 2007»
14 years 6 months ago
Argus: Low-Cost, Comprehensive Error Detection in Simple Cores
We have developed Argus, a novel approach for providing low-cost, comprehensive error detection for simple cores. The key to Argus is that the operation of a von Neumann core cons...
Albert Meixner, Michael E. Bauer, Daniel J. Sorin
MICRO
2007
IEEE
137views Hardware» more  MICRO 2007»
14 years 6 months ago
Implementing Signatures for Transactional Memory
Transactional Memory (TM) systems must track the read and write sets—items read and written during a transaction—to detect conflicts among concurrent transactions. Several TM...
Daniel Sanchez, Luke Yen, Mark D. Hill, Karthikeya...
MICRO
2007
IEEE
129views Hardware» more  MICRO 2007»
14 years 6 months ago
A Framework for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy
Current on-chip block-centric memory hierarchies exploit access patterns at the fine-grain scale of small blocks. Several recently proposed techniques for coherence traffic reduct...
Jason Zebchuk, Elham Safi, Andreas Moshovos