MICRO
2007
IEEE
14 years 6 months ago
2007
IEEE
DRAM memory is a major resource shared among cores in a chip multiprocessor (CMP) system. Memory requests from different threads can interfere with each other. Existing memory acc...
MICRO
2007
IEEE
14 years 6 months ago
2007
IEEE
The recent design shift towards multicore processors has spawned a significant amount of research in the area of program parallelization. The future abundance of cores on a singl...
MICRO
2007
IEEE
14 years 6 months ago
2007
IEEE
MICRO
2007
IEEE
14 years 6 months ago
2007
IEEE
MICRO
2007
IEEE
14 years 6 months ago
2007
IEEE
Addresses suffering from cache misses typically exhibit repetitive patterns due to the temporal locality inherent in the access stream. However, we observe that the number of inte...
MICRO
2007
IEEE
14 years 6 months ago
2007
IEEE
Process variations will greatly impact the stability, leakage power consumption, and performance of future microprocessors. These variations are especially detrimental to 6T SRAM ...
MICRO
2007
IEEE
14 years 6 months ago
2007
IEEE
MICRO
2007
IEEE
14 years 6 months ago
2007
IEEE
Modern chip multiprocessors (CMPs) are designed to exploit both instruction-level parallelism (ILP) within processors and thread-level parallelism (TLP) within and across processo...
MICRO
2007
IEEE
14 years 6 months ago
2007
IEEE
The performance of computer systems varies over the course of their execution. A system may perform well during some parts of its execution and poorly during others. To understand...
MICRO
2007
IEEE
14 years 6 months ago
2007
IEEE
As silicon process technology scales deeper into the nanometer regime, hardware defects are becoming more common. Such defects are bound to hinder the correct operation of future ...