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MICRO
2008
IEEE
83views Hardware» more  MICRO 2008»
14 years 12 days ago
Evaluating the effects of cache redundancy on profit
Abhishek Das, Berkin Özisikyilmaz, Serkan Ozd...
MICRO
2008
IEEE
146views Hardware» more  MICRO 2008»
14 years 12 days ago
A small cache of large ranges: Hardware methods for efficiently searching, storing, and updating big dataflow tags
Dynamically tracking the flow of data within a microprocessor creates many new opportunities to detect and track malicious or erroneous behavior, but these schemes all rely on the...
Mohit Tiwari, Banit Agrawal, Shashidhar Mysore, Jo...
MICRO
2008
IEEE
79views Hardware» more  MICRO 2008»
14 years 12 days ago
Strategies for mapping dataflow blocks to distributed hardware
Distributed processors must balance communication and concurrency. When dividing instructions among the processors, key factors are the available concurrency, criticality of depen...
Behnam Robatmili, Katherine E. Coons, Doug Burger,...
MICRO
2008
IEEE
137views Hardware» more  MICRO 2008»
14 years 12 days ago
Verification of chip multiprocessor memory systems using a relaxed scoreboard
Verification of chip multiprocessor memory systems remains challenging. While formal methods have been used to validate protocols, simulation is still the dominant method used to ...
Ofer Shacham, Megan Wachs, Alex Solomatnikov, Amin...
MICRO
2008
IEEE
107views Hardware» more  MICRO 2008»
14 years 6 months ago
A distributed processor state management architecture for large-window processors
— Processor architectures with large instruction windows have been proposed to expose more instruction-level parallelism (ILP) and increase performance. Some of the proposed arch...
Isidro Gonzalez, Marco Galluzzi, Alexander V. Veid...
MICRO
2008
IEEE
124views Hardware» more  MICRO 2008»
14 years 6 months ago
Token tenure: PATCHing token counting using directory-based cache coherence
Traditional coherence protocols present a set of difficult tradeoffs: the reliance of snoopy protocols on broadcast and ordered interconnects limits their scalability, while dire...
Arun Raghavan, Colin Blundell, Milo M. K. Martin
MICRO
2008
IEEE
106views Hardware» more  MICRO 2008»
14 years 6 months ago
EVAL: Utilizing processors with variation-induced timing errors
Parameter variation in integrated circuits causes sections of a chip to be slower than others. If, to prevent any resulting timing errors, we design processors for worst-case para...
Smruti R. Sarangi, Brian Greskamp, Abhishek Tiwari...
MICRO
2008
IEEE
142views Hardware» more  MICRO 2008»
14 years 6 months ago
NBTI tolerant microarchitecture design in the presence of process variation
—Negative bias temperature instability (NBTI), which reduces the lifetime of PMOS transistors, is becoming a growing reliability concern for sub-micrometer CMOS technologies. Par...
Xin Fu, Tao Li, José A. B. Fortes