Sciweavers

DATE
2005
IEEE
119views Hardware» more  DATE 2005»
14 years 5 months ago
On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips
Multi-site testing is a popular and effective way to increase test throughput and reduce test costs. We present a test throughput model, in which we focus on wafer testing, and co...
Sandeep Kumar Goel, Erik Jan Marinissen
DATE
2009
IEEE
134views Hardware» more  DATE 2009»
14 years 6 months ago
A diagnosis algorithm for extreme space compaction
— During volume testing, test application time, test data volume and high performance automatic test equipment (ATE) are the major cost factors. Embedded testing including builti...
Stefan Holst, Hans-Joachim Wunderlich