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ASPDAC
2010
ACM
183views Hardware» more  ASPDAC 2010»
13 years 10 months ago
Multi-operand adder synthesis on FPGAs using generalized parallel counters
Multi-operand adders, which are also found in parallel multipliers, usually consist of the compression trees which reduce the number of operands per a bit to two, and the carrypro...
Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga
ARITH
2003
IEEE
14 years 5 months ago
Saturating Counters: Application and Design Alternatives
We define a new class of parallel counters, Saturating Counters, which provide the exact count of the inputs that are 1 only if this count is below a given threshold. Such counte...
Israel Koren, Yaron Koren, Bejoy G. Oomman
ARITH
2005
IEEE
14 years 6 months ago
Synthesis of Saturating Counters Using Traditional and Non-Traditional Basic Counters
Saturating counters are a newly defined class of generalized parallel counters that provide the exact number of inputs which are equal to 1 only if this number is below a given t...
Zhaojun Wo, Israel Koren
GLVLSI
2007
IEEE
115views VLSI» more  GLVLSI 2007»
14 years 6 months ago
Novel architectures for efficient (m, n) parallel counters
Parallel counters are key elements in many arithmetic circuits, especially fast multipliers. In this paper, novel architectures and designs for high speed, low power (3, 2), (7, 3...
Sreehari Veeramachaneni, Lingamneni Avinash, Kirth...