VLSISP
2002
13 years 10 months ago
2002
3:2 counters and 4:2 compressors have been widely used for multiplier implementations. In this paper, a fast 5:3 compressor is derived for high-speed multiplier implementations. Th...
FPL
2005
Springer
14 years 4 months ago
2005
Springer
A module generator called Mullet for producing near-optimal parallel multipliers in a technology independent manner is presented. Using this tool, a large number of candidate desi...
ARITH
2007
IEEE
14 years 5 months ago
2007
IEEE
This paper introduces two novel architectures for parallel decimal multipliers. Our multipliers are based on a new algorithm for decimal carry–save multioperand addition that us...
ISCAS
2008
IEEE
14 years 5 months ago
2008
IEEE
— We consider the problem of adding the partial products in the combinational decimal multiplier presented by Lang and Nannarelli. In the original paper this addition is done wit...
DATE
2008
IEEE
14 years 5 months ago
2008
IEEE
Constant-coefficient multipliers are fundamental components in digital signal processing and arithmetic-based systems. Their verification, however, remains difficult and time-cons...