Power consumption within the memory hierarchy grows in importance as on-chip data caches occupy increasingly greater die area. Among dynamic power conservation schemes, horizontal...
—Dynamic programmable logic arrays (PLAs) which are built of the NOR–NOR structure, have been very popular in high performance design because of their high-speed and predictabl...
- This paper describes a novel low-power coding methodology for buses. Ultra deep submicron technology and system-on-chip have resulted in a considerable portion of power consumpti...
Masanori Muroyama, Kosuke Tarumi, Koji Makiyama, H...
This paper presents a multi-objective algorithm for on-line adaptation of a multi-carrier code-division multiple access (MC-CDMA) receiver. A specially tailored Genetic Algorithm ...
Power consumption has become a very important metric and challenging research topic in the design of microprocessors in the recent years. The goal of this work is to improve power...
Frederico Pratas, Georgi Gaydadjiev, Mladen Bereko...
—Server consolidation based on virtualization is a key ingredient for improving power efficiency and resource utilization in cloud computing infrastructures. However, to provide...
Gueyoung Jung, Matti A. Hiltunen, Kaustubh R. Josh...
Electric grids are moving from a centralized single supply chain towards a decentralized bidirectional grid of suppliers and consumers in an uncertain and dynamic scenario. Soon, t...
This paper presents a new logic style, named Current-Mode Differential logic (CMDL), that achieves both high operating speed and low power consumption. Inspired by the low-voltage ...
Content addressable memory (CAM) is frequently used in applications, such as lookup tables, databases, associative computing, and networking, that require high-speed searches due t...
— Low energy consumption is a critical issue in embedded systems design. As the technology feature sizes of SoC (Systems on Chip) become smaller and smaller, the percentage of le...