GLVLSI
2008
IEEE
14 years 1 months ago
2008
IEEE
This paper presents a process variation tolerant, SoC ready, 1GS/s, 6 bit flash analog-to-digital converter (ADC) suitable for integration into nanoscale digital CMOS technologie...
ISQED
2008
IEEE
14 years 6 months ago
2008
IEEE
In this paper we present a parasitic aware, process variation tolerant optimization methodology that may be applied to nanoscale circuits to ensure better yield. A currentstarved ...