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Quasi delay insensitive circuits are functionally independent of delays in gates and wires (except for some particular wires). Such asynchronous circuits offer high robustness but...
This paper addresses the issue of Single-Event Upset (SEU) in quasi delay-insensitive (QDI) asynchronous circuits. We show that an SEU can cause abnormal computations in QDI circu...
—Quasi Delay Insensitive asynchronous logic is a very robust system allowing safe implementations while requiring minimal timing assumptions. Unfortunately the design methodologi...