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VLSI
2005
Springer
14 years 4 months ago
Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits
Quasi delay insensitive circuits are functionally independent of delays in gates and wires (except for some particular wires). Such asynchronous circuits offer high robustness but...
Bertrand Folco, Vivian Brégier, Laurent Fes...
ASYNC
2005
IEEE
90views Hardware» more  ASYNC 2005»
14 years 4 months ago
SEU-Tolerant QDI Circuits
This paper addresses the issue of Single-Event Upset (SEU) in quasi delay-insensitive (QDI) asynchronous circuits. We show that an SEU can cause abnormal computations in QDI circu...
Wonjin Jang, Alain J. Martin
DDECS
2009
IEEE
106views Hardware» more  DDECS 2009»
14 years 5 months ago
Forward and backward guarding in early output logic
—Quasi Delay Insensitive asynchronous logic is a very robust system allowing safe implementations while requiring minimal timing assumptions. Unfortunately the design methodologi...
Charlie Brej, Doug Edwards