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ARVLSI
1995
IEEE
220views VLSI» more  ARVLSI 1995»
14 years 3 months ago
Optimization of combinational and sequential logic circuits for low power using precomputation
Precomputation is a recently proposed logic optimization technique which selectively disables the inputs of a sequential logic circuit, thereby reducing switching activity and pow...
José Monteiro, John Rinderknecht, Srinivas ...
ISQED
2010
IEEE
128views Hardware» more  ISQED 2010»
14 years 5 months ago
Soft error rate determination for nanoscale sequential logic
We analyze the neutron induced soft error rate (SER) by modeling induced error pulse using two parameters, occurrence frequency and probability density function for the pulse widt...
Fan Wang, Vishwani D. Agrawal