Soft error rate determination for nanoscale sequential logic

We analyze the neutron induced soft error rate (SER) by modeling induced error pulse using two parameters, occurrence frequency and probability density function for the pulse width. We extend the analysis to sequential logic and latches and calculate the failures in time (FIT) rate. The analysis is developed for the available background neutron flux data, which is experimentally determined. This, along with the device characteristics, gives the induced pulse parameters. A gate-level algorithm propagates the pulse parameters through logic gates. This algorithm correctly models the logic masking of error pulses. We introduce the concept of latching window that accurately models the temporal masking by sequential elements and present an algorithm for SER analysis of sequential logic. Keywords FIT rate, SEU, SER, Soft error, sequential circuits

• Type: Conference
• Year: 2010
• Where: ISQED
• Authors: Fan Wang, Vishwani D. Agrawal
• Keywords: Error Pulses, Hardware, ISQED 2010, Pulse Parameters, Sequential Logic