Sciweavers

CODES
2004
IEEE
14 years 3 months ago
Benchmark-based design strategies for single chip heterogeneous multiprocessors
Single chip heterogeneous multiprocessors are arising to meet the computational demands of portable and handheld devices. These computing systems are not fully custom designs trad...
JoAnn M. Paul, Donald E. Thomas, Alex Bobrek
CODES
2004
IEEE
14 years 3 months ago
Memory system design space exploration for low-power, real-time speech recognition
The recent proliferation of computing technology has brought added interest to natural I/O interface technologies such as speech recognition. Unfortunately, the computational and ...
Rajeev Krishna, Scott A. Mahlke, Todd M. Austin
CODES
2004
IEEE
14 years 3 months ago
Fast exploration of bus-based on-chip communication architectures
As a result of improvements in process technology, more and more components are being integrated into a single System-on-Chip (SoC) design. Communication between these components ...
Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdha...
CODES
2004
IEEE
14 years 3 months ago
Efficient exploration of on-chip bus architectures and memory allocation
Separation between computation and communication in system design allows the system designer to explore the communication architecture independently of component selection and map...
Sungchan Kim, Chaeseok Im, Soonhoi Ha
CODES
2004
IEEE
14 years 3 months ago
Compiler-directed code restructuring for reducing data TLB energy
Prior work on TLB power optimization considered circuit and architectural techniques. A recent software-based technique for data TLBs has considered the possibility of storing the...
Mahmut T. Kandemir, Ismail Kadayif, Guilin Chen
CODES
2004
IEEE
14 years 3 months ago
Hardware synthesis from coarse-grained dataflow specification for fast HW/SW cosynthesis
This paper concerns automatic hardware synthesis from data flow graph (DFG) specification for fast HW/SW cosynthesis. A node in DFG represents a coarse grain block such as FIR and...
Hyunuk Jung, Soonhoi Ha
CODES
2004
IEEE
14 years 3 months ago
Tuning SoC platforms for multimedia processing: identifying limits and tradeoffs
We present a analytical framework to identify the tradeoffs and performance impacts associated with different SoC platform configurations in the specific context of implementing m...
Alexander Maxiaguine, Yongxin Zhu, Samarjit Chakra...
CODES
2004
IEEE
14 years 3 months ago
A loop accelerator for low power embedded VLIW processors
The high transistor density afforded by modern VLSI processes have enabled the design of embedded processors that use clustered execution units to deliver high levels of performan...
Binu K. Mathew, Al Davis