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ASPDAC
2007
ACM
98views Hardware» more  ASPDAC 2007»
14 years 16 days ago
A Software Technique to Improve Yield of Processor Chips in Presence of Ultra-Leaky SRAM Cells Caused by Process Variation
- Exceptionally leaky transistors are increasingly more frequent in nano-scale technologies due to lower threshold voltage and its increased variation. Such leaky transistors may e...
Maziar Goudarzi, Tohru Ishihara, Hiroto Yasuura
ISCAS
2007
IEEE
167views Hardware» more  ISCAS 2007»
14 years 5 months ago
An Adaptive Sleep Transistor Biasing Scheme for Low Leakage SRAM
— Reducing the leakage power in embedded SRAM memories is critical for low-power applications. Raising the source voltage of SRAM cells in standby mode reduces the leakage curren...
Afshin Nourivand, Chunyan Wang, M. Omair Ahmad
ICCAD
2002
IEEE
80views Hardware» more  ICCAD 2002»
14 years 7 months ago
Minimizing power across multiple technology and design levels
Approaches to achieve low-power and high-speed VLSI's are described with the emphasis on techniques across multiple technology and design levels. To suppress the leakage curr...
Takayasu Sakurai