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We present a procedure to generate short test sequences for synchronous sequential circuits described at the gate level. Short test sequences are important in reducing test applic...
This paper presents a new approach to the automated generation of an initialization sequence for synchronous sequential circuits. Finding an initialization sequence is a hard task...
Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo,...
Testing circuits which do not include a global reset signal requires either complex ATPG algorithms based on 9- or even 256-valued algebras, or some suitable method to generate in...
Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo,...
We present a methodology for the watermarking of synchronous sequential circuits that makes it possible to identify the authorship of designs by imposing a digital watermark on th...