CODES
2008
IEEE
14 years 2 months ago
2008
IEEE
SystemC is widely used for modeling and simulation in hardware/software co-design. Due to the lack of a complete formal semantics, it is not possible to verify SystemC designs. In...
RSP
2005
IEEE
14 years 6 months ago
2005
IEEE
We present an integrated system design environment for SystemC, called SyCE. The system consists of several components for efficient analysis, verification and debugging of Syst...
ACSD
2005
IEEE
14 years 6 months ago
2005
IEEE
We describe a toolbox for the analysis of Systems-on-achip described in SystemC at the transactional level. The tools are able to extract information from SystemC code, and to bui...
ISVLSI
2006
IEEE
14 years 6 months ago
2006
IEEE
Due to increasing design complexity new methodologies for system modeling have been established in VLSI CAD. The SystemC methodology gains a significant reduction of design cycle...
DATE
2006
IEEE
14 years 6 months ago
2006
IEEE
This paper presents an effective approach to formally verify SystemC designs. The approach translates SystemC models into a Petri-Net based representation. The Petri-net model is ...
DDECS
2007
IEEE
14 years 6 months ago
2007
IEEE
This paper proposes debug patterns combined with an intuitive flow to accelerate and simplify the debugging of SystemC designs. A debug pattern provides a formalized procedure to f...