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    TCAD
    1998
    125views more  TCAD 1998»
    BDD-based synthesis of extended burst-mode controllers
    13 years 11 months ago
    BDD-based synthesis of extended burst-mode controllers
    Download  paradise.ucsd.edu
    Abstract—We examine the implications of a new hazard-free combinational logic synthesis method [1], which generates multiplexor-based networks from binary decision diagrams (BDDs...
    Kenneth Y. Yun, Bill Lin, David L. Dill, Srinivas ...
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    TCAD
    1998
    107views more  TCAD 1998»
    Optimizing dominant time constant in RC circuits
    13 years 11 months ago
    Optimizing dominant time constant in RC circuits
    Download  isl.stanford.edu
    — Conventional methods for optimal sizing of wires and transistors use linear resistor-capacitor (RC) circuit models and the Elmore delay as a measure of signal delay. If the RC ...
    Lieven Vandenberghe, Stephen P. Boyd, Abbas A. El ...
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    TCAD
    1998
    86views more  TCAD 1998»
    Fast heuristic and exact algorithms for two-level hazard-free logic minimization
    13 years 11 months ago
    Fast heuristic and exact algorithms for two-level hazard-free logic minimization
    Download  www.cs.columbia.edu
    None of the available minimizers for 2-level hazard-free logic minimization can synthesize very large circuits. This limitation has forced researchers to resort to manual and auto...
    Michael Theobald, Steven M. Nowick
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    TCAD
    1998
    154views more  TCAD 1998»
    Address generation for memories containing multiple arrays
    13 years 11 months ago
    Address generation for memories containing multiple arrays
    Download  www.cecs.uci.edu
    This paper presents techniques for generating addresses for memories containing multiple arrays. Because these techniques rely on the inversion or rearrangement of address bits, t...
    Herman Schmit, Donald E. Thomas
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    TCAD
    1998
    114views more  TCAD 1998»
    Behavioral optimization using the manipulation of timing constraints
    13 years 11 months ago
    Behavioral optimization using the manipulation of timing constraints
    Download  www.cs.ucla.edu
    — We introduce a transformation, named rephasing, that manipulates the timing parameters in control-data-flow graphs (CDFG’s) during the high-level synthesis of data-pathinten...
    Miodrag Potkonjak, Mani B. Srivastava
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    TCAD
    1998
    82views more  TCAD 1998»
    Structural methods for the synthesis of speed-independent circuits
    13 years 11 months ago
    Structural methods for the synthesis of speed-independent circuits
    Download  www.cecs.uci.edu
    Most existing tools for the synthesisof asynchronouscircuits from Signal Transition Graphs (STGs) derive the reachability graph for the calculation of logic equations. This paper ...
    Enric Pastor, Jordi Cortadella, Alex Kondratyev, O...
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    TCAD
    1998
    95views more  TCAD 1998»
    High-precision interconnect analysis
    13 years 11 months ago
    High-precision interconnect analysis
    Download  www.ieeta.pt
    — Integrated circuits have evolved to a stage where interconnections significantly limit their performance and functional complexity. We introduce a set of tools to perform high...
    Rui Martins, Wolfgang Pyka, Rainer Sabelka, Siegfr...
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    TCAD
    1998
    115views more  TCAD 1998»
    Probabilistic modeling of dependencies during switching activity analysis
    13 years 11 months ago
    Probabilistic modeling of dependencies during switching activity analysis
    Download  www.ece.cmu.edu
    —This paper addresses, from a probabilistic point of view, the issue of switching activity estimation in combinational circuits under the zero-delay model. As the main theoretica...
    Radu Marculescu, Diana Marculescu, Massoud Pedram
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    TCAD
    1998
    91views more  TCAD 1998»
    Cost-free scan: a low-overhead scan path design
    13 years 11 months ago
    Cost-free scan: a low-overhead scan path design
    Download  www.cecs.uci.edu
    Conventional scan design imposes considerable area and delay overhead by using larger scan ip- ops and additional scan wires without utilizing the functionality of the combinatio...
    Chih-Chang Lin, Malgorzata Marek-Sadowska, Mike Ti...
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    TCAD
    1998
    125views more  TCAD 1998»
    Test-point insertion: scan paths through functional logic
    13 years 11 months ago
    Test-point insertion: scan paths through functional logic
    Download  www.pld.ttu.ee
    —Conventional scan design imposes considerable area and delay overheads. To establish a scan chain in the test mode, multiplexers at the inputs of flip-flops and scan wires are...
    Chih-Chang Lin, Malgorzata Marek-Sadowska, Kwang-T...
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