JCP
2008
13 years 11 months ago
2008
Sleep transistors in industrial power-gating designs are custom designed with an optimal size. Consequently, sleep transistor P/G network optimization becomes a problem of finding ...
ISLPED
1995
ACM
14 years 3 months ago
1995
ACM
Thispaper proposes a method for achieving low-power control-logic modules using a combination of CMOS complex gate reorganization, transistor size optimization, and transistor lay...
ISLPED
1995
ACM
14 years 3 months ago
1995
ACM
We consider the problem of transistor sizing in a static CMOS layout to minimizethe power consumption of the circuit subject to a given delay constraint. Based on our characteriza...
ASPDAC
1999
ACM
14 years 3 months ago
1999
ACM
In this paper we consider transistor sizing to reduce crosstalk. First, crosstalk noise dependency on wire width, wire spacing, driver and receiver sizes are discussed, and valida...
DATE
2002
IEEE
14 years 4 months ago
2002
IEEE
Transistor tapering is a widely used technique applied to optimize the geometries of CMOS transistors in highperformance circuit design with a view to minimizing the delay of a FE...