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VLSID
2008
IEEE
142views VLSI» more  VLSID 2008»
14 years 12 months ago
Temperature and Process Variations Aware Power Gating of Functional Units
Technology scaling has resulted in an exponential increase in the leakage power as well as the variations in leakage power of fabricated chips. Functional units (FUs), like Intege...
Deepa Kannan, Aviral Shrivastava, Vipin Mohan, Sar...
VLSID
2008
IEEE
151views VLSI» more  VLSID 2008»
14 years 12 months ago
Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-Chip
Worst-case execution time (WCET) analysis and, in general, the predictability of real-time applications implemented on multiprocessor systems has been addressed only in very restri...
Alexandru Andrei, Petru Eles, Zebo Peng, Jakob Ros...
VLSID
2008
IEEE
128views VLSI» more  VLSID 2008»
14 years 12 months ago
A Novel Approach to Compute Spatial Reuse in the Design of Custom Instructions
In the automatic design of custom instruction set processors, there can be a very large set of potential custom instructions, from which a few instructions are required to be chos...
Nagaraju Pothineni, Anshul Kumar, Kolin Paul
VLSID
2008
IEEE
166views VLSI» more  VLSID 2008»
14 years 12 months ago
Exploring the Processor and ISA Design for Wireless Sensor Network Applications
Power consumption, physical size, and architecture design of sensor node processors have been the focus of sensor network research in the architecture community. What lies at the ...
Shashidhar Mysore, Banit Agrawal, Frederic T. Chon...
VLSID
2008
IEEE
225views VLSI» more  VLSID 2008»
14 years 12 months ago
Formal Verification of a Public-Domain DDR2 Controller Design
This paper demonstrates a formal verificationplanning process and presents associated verification strategy that we believe is an essential (yet often neglected) step in an ASIC o...
Abhishek Datta, Vigyan Singhal
VLSID
2008
IEEE
117views VLSI» more  VLSID 2008»
14 years 12 months ago
Single Event Upset: An Embedded Tutorial
Abstract-- With the continuous downscaling of CMOS technologies, the reliability has become a major bottleneck in the evolution of the next generation systems. Technology trends su...
Fan Wang, Vishwani D. Agrawal
VLSID
2008
IEEE
138views VLSI» more  VLSID 2008»
14 years 12 months ago
Memory Architecture Exploration Framework for Cache Based Embedded SOC
Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and l...
T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindaraj...
VLSID
2008
IEEE
83views VLSI» more  VLSID 2008»
14 years 12 months ago
Efficient Linear Macromodeling via Discrete-Time Time-Domain Vector Fitting
We present a discrete-time time-domain vector fitting algorithm, called TD-VFz, for rational function macromodeling of port-to-port responses with discrete time-sampled data. The ...
Chi-Un Lei, Ngai Wong
VLSID
2008
IEEE
95views VLSI» more  VLSID 2008»
14 years 12 months ago
A New Threshold Voltage Model for Omega Gate Cylindrical Nanowire Transistor
In this work, for the first time, we present a physically based analytical threshold voltage model for omega gate silicon nanowire transistor. This model is developed for long cha...
Biswajit Ray, Santanu Mahapatra
VLSID
2008
IEEE
120views VLSI» more  VLSID 2008»
14 years 12 months ago
Continuous Frequency Adjustment Technique Based on Dynamic Workload Prediction
Real-time embedded systems increasingly rely on dynamic power management to balance between power and performance goals. In this paper, we present a technique for continuous frequ...
Hwisung Jung, Massoud Pedram