VTS
1996
IEEE
14 years 3 months ago
1996
IEEE
This paper presents an innovative method for inserting test points in the circuit-under-test to obtain complete fault coverage for a specified set of test patterns. Rather than us...
VTS
1996
IEEE
14 years 3 months ago
1996
IEEE
VTS
1996
IEEE
14 years 3 months ago
1996
IEEE
Designing a testable circuit is often a two step process. First, the circuit is designed to conform to the functional specifications. Then, the testability aspects are added. By t...
VTS
1996
IEEE
14 years 3 months ago
1996
IEEE
In this paper we investigate optimal voltage testing approaches for physically-based faults in CMOS circuits. We describe the general nature of the problem and then focus on two f...
VTS
1996
IEEE
14 years 3 months ago
1996
IEEE
In this paper, we for the rst time present experimental evidence that the die surface can act as an RC interconnect, becoming an important factor in determining the voltage of a o...
VTS
1996
IEEE
14 years 3 months ago
1996
IEEE
A fault-oriented sequential circuit test generator is described in which various types of distinguishing sequences are derived, both statically and dynamically, to aid the test ge...
VTS
1996
IEEE
14 years 3 months ago
1996
IEEE
VTS
1996
IEEE
14 years 3 months ago
1996
IEEE
Some weak static CMOS chips can be detected by testing them with a very low supply voltage -- between 2 and 2.5 times the threshold voltage Vt of the transistors. A weak chip is o...
VTS
1996
IEEE
14 years 3 months ago
1996
IEEE