Revisiting the linear programming framework for leakage power vs. performance optimization

— This paper revisits and extends a general linear programming(LP) formulation to exploit multiple knobs such as multi-Lgate footprint-compatible libraries and post-layout Lgatebiasing to minimize total leakage power under timing constraints. We minimize positive timing slack for each cell according to its leakage vs. delay sensitivity, so that unnecessary leakage power consumption is saved without degrading circuit performance. A key difference between our work and previous works is that we pre-process timing libraries to estimate the linear relation – in every slew-load condition – between the gate delay and gate length by linear fitting; we then optimize total leakage power by estimating the optimal gate length for each gate using fast linear programming. With a 65GP industry testbed, and directly comparing with commercial tools, we show the QOR and runtime advantages of our method for the multiLgate and Lgate-biasing knobs. We also show a promising application to circuit tim...

• Type: Conference
• Year: 2009
• Where: ISQED
• Authors: Kwangok Jeong, Andrew B. Kahng, Hailong Yao
• Keywords: Hardware, ISQED 2009, Leakage Power, Timing Constraints, Total Leakage Power