Study of Floating Fill Impact on Interconnect Capacitance

It is well known that fill insertion adversely affects total and coupling capacitance of interconnects. While grounded fill can be extracted by full-chip extractors, floating fill can be reliably extracted by 3D field solvers only. Due to poor understanding of the impact of floating fill on capacitance, designers insert floating fill conservatively. In this paper we study the impact of floating fill insertion on coupling and total capacitance when the fill geometry, and both the interconnects between which the capacitance is measured are on the same layer. We show that the capacitance with same-layer neighboring interconnects is a large fraction of total capacitance, and that it is significantly affected by fill geometries on the same layer. We analyze the effect of fill configuration parameters such as fill size, fill location, interconnect width, interconnect spacing, etc. and consider edge effects and effects occurring due to insertion of several fill geometries ...

• Type: Conference
• Year: 2006
• Where: ISQED
• Authors: Andrew B. Kahng, Kambiz Samadi, Puneet Sharma
• Keywords: Capacitance, Coupling Capacitance, Hardware, ISQED 2006, Total Capacitance