DAC
2005
ACM
14 years 1 months ago
2005
ACM
In this paper, we propose a new sensitivity based, statistical gate sizing method. Since circuit optimization effects the entire shape of the circuit delay distribution, it is dif...
ICCAD
2000
IEEE
14 years 3 months ago
2000
IEEE
ct Static timing analysis has traditionally used the PERT method for identifying the critical path of a digital circuit. Due to the influence of the slope of a signal at a particul...
IOLTS
2005
IEEE
14 years 5 months ago
2005
IEEE
With the aggressive scaling of the CMOS technology parametric variation of the transistor threshold voltage causes significant spread in the circuit delay as well as leakage spect...
ASPDAC
2006
ACM
14 years 5 months ago
2006
ACM
- One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In this paper, we propose a delay modeling and static timing analysis (STA) methodology ta...
ISQED
2007
IEEE
14 years 5 months ago
2007
IEEE
According to the current trend of increasing variations in process technologies and thus in performance, the conservative worst-case design will not work since design margins can ...