25 search results - page 1 / 5 » An FPGA design of AES encryption circuit with 128-bit keys |
GLVLSI
2005
IEEE
14 years 4 months ago
2005
IEEE
This paper addresses a pipelined partial rolling (PPR) architecture for the AES encryption. The key technique is the PPR architecture, which is suitable for FPGA implementation. U...
IEICET
2006
13 years 11 months ago
2006
DAC
2001
ACM
14 years 12 months ago
2001
ACM
: Fault-based side channel cryptanalysis is very effective against symmetric and asymmetric encryption algorithms. Although straightforward hardware and time redundancy based concu...
SACRYPT
2000
Springer
14 years 2 months ago
2000
Springer
We present a new 128-bit block cipher called Camellia. Camellia supports 128-bit block size and 128-, 192-, and 256-bit keys, i.e. the same interface specifications as the Advanced...
CHES
2003
Springer
14 years 4 months ago
2003
Springer
Abstract. In this paper a compact FPGA architecture for the AES algorithm with 128-bit key targeted for low-cost embedded applications is presented. Encryption, decryption and key ...