Power Supply Noise-Aware Scheduling and Allocation for DSP Synthesis

As technology scales down, power supply noise is becoming a performance and reliability bottleneck in modern VLSI. We propose a power supply noise-aware design methodology for high-level synthesis. By evaluating power supply noise in the early design stage, the proposed method generates schedule and resource allocation with a floorplan such that the power supply noise is minimized. To achieve the goal, we formulated the problem using a genetic algorithm. Compared to designs that do not consider supply noise, the proposed methodology reduces power supply noise up to 44%.

• Type: Conference
• Year: 2005
• Where: ISQED
• Authors: Dongku Kang, Yiran Chen, Kaushik Roy
• Keywords: Hardware, ISQED 2005, Methodology Reduces Power, Power Supply Noise, Supply Noise-aware Design