Analysis and Design of LVTSCR-based EOS/ESD Protection Circuits for Burn-in Environment

As technology feature size is reduced, ESD becomes one of the dominant failure modes due to the lower gate oxide breakdown voltage. Also, the holding voltage of LVTSCR devices is reduced with operating temperature increase. As a result, during stress testing (burn-in), the risk of latch-up in LVTSCR is extremely high. In this paper, a new latch-up free LVTSCR-based protection circuit is proposed. It can be reliably used in sub-0.18 um CMOS technologies and burnin environment. The proposed ESD circuit has higher

• Type: Conference
• Year: 2005
• Where: ISQED
• Authors: Oleg Semenov, H. Sarbishaei, Manoj Sachdev
• Keywords: Dominant Failure Modes, Hardware, ISQED 2005, Oxide Breakdown Voltage, Technology Feature Size