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28

VTS
2005
IEEE

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Segmented Addressable Scan Architecture

14 years 4 months ago

Segmented Addressable Scan Architecture

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This paper presents a test architecture that addresses multiple problems faced in digital IC testing. These problems are test data volume, test application time, test power consumption, and tester channel requirements. With minimal hardware overhead, the architecture provides at least an order of magnitude reduction to each of the above problems. The architecture relies on scan chain segmentation and multiple-hot decoders.

Ahmad A. Al-Yamani, Erik Chmelar, Mikhail Grinchuc

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Added	25 Jun 2010
Updated	25 Jun 2010
Type	Conference
Year	2005
Where	VTS
Authors	Ahmad A. Al-Yamani, Erik Chmelar, Mikhail Grinchuck

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