Sciweavers

Free Online Productivity Tools i2Speak i2Symbol i2OCR iTex2Img iWeb2Print iWeb2Shot i2Type iPdf2Split iPdf2Merge i2Bopomofo i2Arabic i2Style i2Image i2PDF iLatex2Rtf Sci2ools

30

PATMOS
2004
Springer

favoriteEmaildiscussreport

112views Modeling and Simulation» more PATMOS 2004»

Leakage Reduction at the Architectural Level and Its Application to 16 Bit Multiplier Architectures

14 years 4 months ago

Leakage Reduction at the Architectural Level and Its Application to 16 Bit Multiplier Architectures

Download www2.informatik.uni-jena.de

Christian Schuster, Jean-Luc Nagel, Christian Pigu

Real-time Traffic

PATMOS 2004 |

claim paper

Related Content

» Sign bit reduction encoding for low power applications

» The Chinese Remainder Theorem and its Application in a HighSpeed RSA Crypto Chip

» Poweraware pipelined multiplier design based on 2dimensional pipeline gating

Post Info
More Details (n/a)

Added	02 Jul 2010
Updated	02 Jul 2010
Type	Conference
Year	2004
Where	PATMOS
Authors	Christian Schuster, Jean-Luc Nagel, Christian Piguet, Pierre-André Farine

Comments (0)