Power Aware Dividers in FPGA

This paper surveys different implementations of dividers on FPGA technology. A special attention is paid on ATP (area-time-power) trade-offs between restoring, non-restoring, and SRT dividers algorithms for different operand widths, remainder representations, and radices. Main results show that SRT radix-2 present the best ATP figure. In combinational implementation, an important power improvement, - up to 51% - with respect to traditional nonrestoring implementations is obtained. Moreover, up to 93% power improvement can be achieved if pipelining is implemented. Finally, the sequential implementation is another important way to reduce the consumption in more than 89 %.

• Type: Conference
• Year: 2004
• Where: PATMOS
• Authors: Gustavo Sutter, Jean-Pierre Deschamps, Gery Bioul, Eduardo I. Boemo
• Keywords: Important Power Improvement, PATMOS 2004, Power Improvement, SRT Dividers Algorithms