Industrial Experience with Adoption of EDT for Low-Cost Test without Concessions

This paper discusses the adoption of Embedded Deterministic Test (EDT) at Infineon Technologies as a means to reduce the cost of manufacturing test without compromising test quality. The System-onChip (SoC) design flow and the changes necessary to successfully implement EDT are presented. Experimental results for three SoC designs targeted for automotive, wireless, and data communication applications are provided. These results demonstrate that EDT, with no performance impact, little area overhead, and minimal impact to the flow, results in a significant reduction of scan test data volume and scan test time while maintaining the test quality levels.

• Type: Conference
• Year: 2003
• Where: ITC
• Authors: Frank Poehl, Matthias Beck, Ralf Arnold, Peter Muhmenthaler, Nagesh Tamarapalli, Mark Kassab, Nilanjan Mukherjee, Janusz Rajski
• Keywords: Embedded Deterministic Test, Hardware, ITC 2003, Scan Test, Test Quality