DATE
2002
IEEE
14 years 5 months ago
2002
IEEE
As technology scales toward deep submicron, on-chip interconnects are becoming more and more sensitive to noise sources such as power supply noise, crosstalk, radiation induced ef...
DATE
2010
IEEE
14 years 5 months ago
2010
IEEE
: Scaling down in very deep submicron (VDSM) technologies increases the delay, power consumption of on-chip interconnects, while the reliability and yield decrease. In high perform...
ISCA
2005
IEEE
14 years 6 months ago
2005
IEEE
This paper examines the area, power, performance, and design issues for the on-chip interconnects on a chip multiprocessor, attempting to present a comprehensive view of a class o...
DSN
2006
IEEE
14 years 6 months ago
2006
IEEE
The advent of deep sub-micron technology has exacerbated reliability issues in on-chip interconnects. In particular, single event upsets, such as soft errors, and hard faults are ...
VLSID
2002
IEEE
15 years 1 months ago
2002
IEEE
The improved T and improved n models are proposed for onchip interconnect macromodeling. Using global approximations, simple approximation frames are derived and applied to modeli...
DAC
2003
ACM
15 years 1 months ago
2003
ACM
Interconnects have been shown to be a dominant source of energy consumption in modern day System-on-Chip (SoC) designs. With a large (and growing) number of electronic systems bei...