Sciweavers

    ASPDAC
    1999
    ACM
    105views Hardware» more  ASPDAC 1999»

    Clock Period Minimization of Semi-Synchronous Circuits by Gate-Level Delay Insertion

    14 years 3 months ago
    Clock Period Minimization of Semi-Synchronous Circuits by Gate-Level Delay Insertion
    Download  www.lab.ss.titech.ac.jp
    Tomoyuki Yoda, Atsushi Takahashi, Yoji Kajitani
    claim paper
    Added 02 Aug 2010
    Updated 02 Aug 2010
    Type Conference
    Year 1999
    Where ASPDAC
    Authors Tomoyuki Yoda, Atsushi Takahashi, Yoji Kajitani
    Comments (0)
    Explore & Download
    Proceedings Preprints Top 5 Ranked Papers Publications Books Software Tutorials Presentations Lectures Notes Datasets
    Productivity Tools
    International On-screen Keyboard Graphical Social Symbols OCR Text Recognition CSS3 Style Generator Web Page to PDF Web Page to Image PDF Split PDF Merge Latex Equation Editor Sci2ools
    Document Tools
    PDF to Text PDF to Postscript PDF to Thumbnails Excel to PDF Word to PDF Postscript to PDF PowerPoint to PDF Latex to Word Repair Corrupted PDF
    Image Tools
    JPG to PS JPG to PDF Extract Images from PDF Image Converter
    Sciweavers
    About Community Cookies Privacy Policy Terms of Use

    Copyright © Sciweavers LLC, 2009-2024, USA.