2 search results - page 1 / 1 » Clock Period Minimization of Semi-Synchronous Circuits by Ga... |
ASPDAC
1999
ACM
15 years 7 months ago
1999
ACM
115
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DAC
2005
ACM
16 years 4 months ago
2005
ACM
The race conditions often limit the smallest feasible clock period that the optimal clock skew scheduling can achieve. Therefore, the combination of clock skew scheduling and dela...