Minimal Length Diagnostic Tests for Analog Circuits using Test History

In this paper we propose an efficient transient test generation method to comprehensively test analog circuits using minimum test time. A divide and conquer strategy is formulated to sequentially synthesize the test stimulus for the entire duration of test. We use a novel measurement procedure to resolve ambiguities in the present measurement sample by using class association information from the previous samples. This sequential formulation of test generation problem enables fault dropping and greatly reduces simulation and optimization effort. Additionally, this method is immune to noise and tests can be easily calibrated for use in hardware testers.

• Type: Conference
• Year: 1999
• Where: DATE
• Authors: Alfred V. Gomes, Abhijit Chatterjee
• Keywords: DATE 1999, Hardware, Minimum Test Time, Test Generation, Test Generation Method