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    ISLPED
    1998
    ACM
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    A power optimization method considering glitch reduction by gate sizing

    14 years 3 months ago
    A power optimization method considering glitch reduction by gate sizing
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    Masanori Hashimoto, Hidetoshi Onodera, Keikichi Ta
    claim paper
    Added 05 Aug 2010
    Updated 05 Aug 2010
    Type Conference
    Year 1998
    Where ISLPED
    Authors Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru
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