An efficient technique for device and interconnect optimization in deep submicron designs

In this paper, we formulate a new class of optimization problem, named the general CH-posynomial program, and reveal the general dominance property. We propose an efcient algorithm based on the extended local re nement operation to compute lower and upper bounds of the exact solution to the general CH-posynomial program. We apply the algorithm to solve the simultaneous transistor and interconnect sizing STIS problem under the table-based device model, and the global interconnect sizing and spacing GISS problem with consideration of the crosstalk capacitance. Experiment results show that our algorithm can handle many device and interconnect modeling issues in deep submicron designs and is very e cient.

• Type: Conference
• Year: 1998
• Where: ISPD
• Authors: Jason Cong, Lei He
• Keywords: General Ch-posynomial Program, General Dominance Property, Hardware, ISPD 1998, Table-based Device Model