Testable Design and Testing of MCMs Based on Multifrequency Scan

In this paper, we present a novel and efticient approach to test MCM at the module as well as chip levels. Our design incorporates the concept of the multifrequency test method and the smart substrate to provide two levels at speed test. The IEEE 1149.1 boundary scan standard is used to ofSer the necessity of controllability and observability. Part of the boundary scan cells used in the chip level are modified toform the module level scan chain. Using the chip level boundary scan cells to provide both chip and module level testings, it not only decreases area overhead but also reduces extra delay introduced by the addition of test circuits. The contribution of this paper is to provide an MCM design for testability strategy which has the capability to detect performance defects as well as static faults will small delay and low overhead.

• Type: Conference
• Year: 1996
• Where: ATS
• Authors: Wang-Dauh Tseng, Kuochen Wang
• Keywords: ATS 1996, Boundary Scan, Boundary Scan Cells, Chip Level, Hardware