A Combined DOE-ILP Based Power and Read Stability Optimization in Nano-CMOS SRAM

A novel design approach for simultaneous power and stability (static noise margin, SNM) optimization of nanoCMOS static random access memory (SRAM) is presented. A 45nm single-ended seven transistor SRAM is used as a case study. The SRAM is subjected to a dual-VT h assignment using a novel combined Design of Experiments and Integer Linear Programming (DOE-ILP) algorithm, resulting in 50.6% power reduction (including leakage) and 43.9% increase in the read SNM. The process variation analysis of the optimal SRAM carried out considering twelve device parameters shows the robustness of the design.

• Type: Conference
• Year: 2010
• Where: VLSID
• Authors: Garima Thakral, Saraju P. Mohanty, Dhruva Ghai, Dhiraj K. Pradhan
• Keywords: Static Noise Margin, Static Random Access Memory, Transistor Sram, VLSI, VLSID 2010